The present invention relates to a field effect transistor and a fabrication method thereof, a semiconductor device and a fabrication method thereof, a logic circuit including the semiconductor device, and a semiconductor substrate, and particularly to a field effect transistor in which a source/a drain are formed in a silicon layer having a strain effect and a fabrication method thereof, a semiconductor device including the field effect transistor and a fabrication method thereof, a logic circuit including the semiconductor device, and a semiconductor substrate on which the field effect transistor, the semiconductor device, or the logic circuit is formed.
With the advance of a technique of forming a thin film made from a group IV semiconductor material such as silicon/silicon germanium, devices using materials having a strain effect have been allowed to be fabricated, and at present, studies are being extensively made to realize high function and low voltage devices using materials having a strain effect.
The strain effect means a phenomenon that in a thin film semiconductor applied with a stress, an energy band is distorted to change an effective mass of carriers. A semiconductor thin film having such a strain effect has been allowed to be realized by forming a multi-layered film such as silicon/silicon germanium in such a manner as to control an inner stress of the film using a molecular beam epitaxy technique or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process. High quality MOS based devices or sensors have been also developed by controlling a difference in band gap or a film strain through hetero-junction.
A silicon film on a SOI (Silicon on Insulator) substrate formed using a technique of forming a single crystal silicon film by zone melting or irradiation of argon ion laser is applied with a tensile stress. Besides, a silicon film on a SOS (Silicon on Sapphire) substrate is applied with a compressive stress. As a result, for the former silicon film, the mobility of electrons becomes larger and for the latter silicon film, the mobility of positive holes becomes larger. In other words, for the former, the mobility of positive holes becomes smaller and for the latter, the mobility of electrons becomes smaller
For a silicon based MOS (Metal-Oxide-Semiconductor) transistor, by depositing a silicon film on an epitaxial layer made from silicon germanium whose stress is relaxed, the mobility of electrons is made larger by a tensile stress (which is strictly explained such that six regenerated bands are divided into two bands different in effective mass of electrons). Besides, in the case of formation of silicon germanium containing germanium in a large amount (that is, a germanium rich silicon germanium), the mobility of positive holes are made larger by a compressive stress.
In a MOS transistor prepared such that the stress of a channel layer is controlled by forming a multi-layered film based on the above property of the strain effect silicon layer, a high mutual conductance [gm (mobility)] can be obtained. Such a p-type MOS is disclosed in Appl. Phys. Letter (USA), 63 (1993) S. P. Voinigensen et al., p 660 and IEEE Electronic Devices (USA), 43 (1996) L. H. Jiang and R. G. Elliman, p 97. Further, an nMOS is disclosed in Appl. Phys. Letter (USA), 64 (1994) K. Ismail et al., p3124 and IEDM 94-37 (USA), (1994) J. Welser et al.
A pass-transistor, as the advanced high performance logic operable at a low voltage, has been proposed in the field of the advanced applied technology such as a CPU (Central Processing Unit) or MPEG (Moving Picture Experts Group). In such a logic circuit, an nMOS transistor as a main component requires such a high level characteristic as to exhibit a high mutual conductance with a low voltage operation. Besides, a pMOS transistor is used for pre-charge or the like and has less number of elements. That is, the pMOS transistor does not require a higher operational speed as compared with the nMOS, and therefore, it is not disadvantageous from the areal viewpoint even if the performance is determined by adjustment of the channel width W.
In the case where the above-described related art pMOS or nMOS transistor is used in an application requiring a high performance at a low voltage, however, there occurs a problem of a junction leak of the transistor because the junction of the source/drain is positioned in a silicon germanium layer having a small band gap or formed at an interface of silicon/silicon germanium.